Methods of forming semiconductor constructions

ABSTRACT

The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

TECHNICAL FIELD

The invention pertains to methods of forming semiconductorconstructions, and in particular aspects pertains to methods whichinclude formation of semiconductor constructions and passivation of theconstructions.

BACKGROUND OF THE INVENTION

Semiconductor constructions can comprise numerous electricallyinsulative structures, including, for example, gate dielectric,capacitor dielectric, isolation regions, etc. Frequently, at least someof the insulative structures will have some hydrogen incorporatedtherein.

The hydrogen traditionally utilized is the naturally-occurring isotopicmixture, which is about 99.985%¹H, and about 0.015%²H (deuterium).

A continuing goal in semiconductor processing is to produce robustdevices in higher levels of integration. In some aspects, the inventiondescribed and claimed in this disclosure extends deuterium-enrichmenttechnologies to improve stability of various insulative materials, andto improve longevity of devices comprising such insulative materials.

SUMMARY OF THE INVENTION

In one aspect, the invention encompasses a method of forming asemiconductor construction which includes two or more of the followingfive steps in any order relative to one another: (1) at least a portionof a first gate oxide is formed by exposure of a semiconductor materialto deuterium-enriched steam; (2) at least a portion of a second gateoxide is formed by exposure of a semiconductor material todeuterium-enriched steam; (3) at least a portion of an oxide is formedover a defined location of a conductively-doped region of asemiconductor material by exposure of the semiconductor material todeuterium-enriched steam; (4) at least a portion of an isolation regionis formed by exposure of a semiconductive material to deuterium-enrichedsteam; and (5) a semiconductor assembly is subjected to an anneal at atemperature of greater than or equal to about 350° C. while exposing theassembly to a deuterium-enriched ambient (the ambient can comprisedeuterium-enriched molecular hydrogen in combination with a carrier,such as nitrogen). The five step process can include multi-gateprocesses, or can include methods in which only a single gate is formed.Also, the process can include aspects for using deuterium-enriched steamduring re-oxidation following gate patterning and an etch of asacrificial oxide. In some aspects, methodology of the present inventioncan be incorporated into fabrication of any suitable transistorstructure, including planar and non-planar structures. For instance,methodology of the present invention can be incorporated intofabrication of multi-gate devices, finFET devices, recessed accessdevices, gate-surround (e.g., gate-all-around) vertical transistors,etc. Devices having large interface areas can significantly benefit frompassivation achieved through methodologies of the present invention.

In one aspect, the invention encompasses a method of forming andpassivating a semiconductor construction. One or more oxides are formedover a semiconductor substrate by exposing semiconductor material of thesubstrate to deuterium-enriched steam. The semiconductor substrate withthe one or more oxides thereover is defined to be at least a portion ofa semiconductor construction. After the one or more oxides are formed,the semiconductor construction is subjected to an anneal at atemperature of greater than or equal to about 350° C. (and typicallyless than 525° C.) while exposing the construction to adeuterium-enriched ambient. The oxides can be referred to as “deuteratedoxides” and can include, for example, gate oxide, re-oxidation stops,and thin buffer oxides (such as silicon dioxide) utilized in conjunctionwith high-k dielectric materials (such as, for example, hafnium oxide,aluminum oxide, etc.).

In one aspect, the invention encompasses another method of forming andpassivating a semiconductor construction. At least one gate oxide isformed over a semiconductor substrate by exposing semiconductivematerial of the substrate to deuterium-enriched steam. At least oneisolation region is formed by initially forming a trench in thesemiconductive material of the substrate, and subsequently exposing thesemiconductive material within the trench to a deuterium-enriched steamto form an oxide liner within the trench. A semiconductor substratehaving the at least one gate oxide and at least one isolation regionthereover is defined to be at least a portion of a semiconductorconstruction. The semiconductor construction is subjected to an annealat a temperature of greater than or equal to about 350° C. whileexposing the semiconductor construction to a deuterium-enriched ambientduring or after final passivation.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic, cross-sectional view of a fragment of asemiconductor construction illustrating various structures which can beformed in accordance with exemplary aspects of the present invention.

FIG. 2 is a diagrammatic, cross-sectional view of a fragment of asemiconductor construction shown at a preliminary processing stage of anexemplary method of the present invention.

FIG. 3 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 2.

FIG. 4 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 3.

FIG. 5 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 4.

FIG. 6 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 5.

FIG. 7 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 6.

FIG. 8 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 7.

FIG. 9 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 8.

FIG. 10 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 9.

FIG. 11 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 10.

FIG. 12 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 11.

FIG. 13 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 12.

FIG. 14 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 13. The wafer fragment of FIG. 14 isidentical to that previously described with reference to FIG. 1.

FIG. 15 is a view of the FIG. 2 wafer fragment shown at a processingstage subsequent to that of FIG. 14.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

The invention includes aspects in which deuterium-enriched steam isutilized during formation of various oxides associated with asemiconductor construction, as well as aspects in which adeuterium-enriched ambient is utilized during passivation of asemiconductor construction. It is found that synergistic effects occurwhen multiple oxides are formed utilizing deuterium-enriched steam, andalso that synergistic effects are observed when passivation with adeuterium-enriched ambient follows such oxide formation. In other words,it is observed that there will be some improvement gained by forming aparticular oxide from deuterium-enriched steam, and additionalimprovement obtained by forming another oxide from deuterium-enrichedsteam, but that the combined improvement from forming both oxides fromdeuterium-enriched steam will unexpectedly be greater than a simple sumof the improvements obtained in isolation from one another. Similarly,it is found that the utilization of a deuterium-enriched ambient duringpassivation will provide some improvement to the properties of variousoxides, and that the coupling of passivation in a deuterium-enrichedambient with the formation of oxides from deuterium-enriched steamadvantageously provides additional improvement beyond a simple sum ofthe individual improvements obtained by utilizing deuterium-enrichedsteam oxidation and deuterium-enriched ambient passivation.

An exemplary semiconductor construction 10 is shown in FIG. 1 todiagrammatically illustrate some of the various oxides which can beformed and treated in exemplary aspects of the present invention.

Construction 10 comprises a semiconductor substrate 12. Substrate 12can, for example, comprise, consist essentially of, or consist ofmonocrystalline silicon lightly-doped with a background dopantconcentration. To aid in interpretation of the claims that follow, theterms “semiconductive substrate” and “semiconductor substrate” aredefined to mean any construction comprising semiconductive material,including, but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above.

A pair of transistor devices 14 and 16 are supported by substrate 12,and electrically isolated from one another by an isolation region 18.

The transistor constructions 14 and 16 comprise electrically conductivetransistor gates 20 and 22, respectively. Such transistor gates cancomprise one or more suitable electrically conductive compositions,including, for example one or more of, various metals, metal compounds(such as, for example, metal silicides), and conductively-doped silicon.

Transistor gate 20 is spaced from an upper surface of substrate 12 by agate dielectric 24, and transistor gate 22 is spaced from an uppersurface of substrate 12 by a gate dielectric 26. In the shown aspect ofthe invention, gate dielectric 26 is substantially thicker than gatedielectric 24. Gate dielectric 24 can have a thickness of, for example,about 25 Å to about 40 Å; and gate dielectric 26 can have a thicknessof, for example, from about 50 Å to about 70 Å. Accordingly, gatedielectric 26 can be at least about 15 Å thicker than gate dielectric24. The difference in thickness of the gate dielectrics can enable thethreshold voltages of devices 14 and 16 to be tailored to be differentfrom one another. The gate dielectric materials 24 and 26 comprise,consist essentially of, or consist of silicon dioxide, and can be formedutilizing a deuterium-enriched steam as discussed below with referenceto FIGS. 6-10.

The transistor devices 14 and 16 comprise conductively-dopedsource/drain regions within the substrate 12 proximate the gates 20 and22. Specifically, transistor device 14 comprises a pair of source/drainregions 28 proximate gate 20, and transistor device 16 comprises a pairof source/drain regions 30 proximate gate 22. The source/drain regions28 comprise heavily-doped portions 27 and lightly-doped portions 29, andsimilarly the source/drain regions 30 comprise heavily-doped portions 31and lightly-doped portions 33.

The source/drain regions correspond to conductively-doped diffusionregions formed within the semiconductor material of substrate 12, andcan be either n-type or p-type. For instance, heavily-doped regions 27of source/drain regions 28 can be either n-type or p-type, andlightly-doped regions 29 can be either the same conductivity type asheavily-doped regions 27 or an opposite conductivity type. Similarly,heavily-doped regions 31 of source/drain regions 30 can be either n-typeor p-type, and lightly-doped regions 33 can be either the sameconductivity type as heavily-doped regions 31 or an oppositeconductivity type. Further, as will be recognized by persons of ordinaryskill in the art, a source/drain region (such as the region 30) cancomprise multiple lightly-doped regions associated with a singleheavily-doped region, with one or more of the lightly-doped regionshaving the same conductivity type as the heavily-doped region, and oneor more of the lightly-doped regions having an opposite conductivitytype as the heavily-doped region.

Dielectric material 40 is formed over upper surfaces ofconductively-doped diffusion regions corresponding to source/drains 28,and also extends along sidewall surfaces of gate 20. The dielectricmaterial 40 is shown merging with gate dielectric 24, and accordingly isshown comprising the same composition as gate dielectric 24. Dielectricmaterial 40 can thus comprise, consist essentially of, or consist ofsilicon dioxide, and in particular aspects will be formed by oxidationof silicon-containing surfaces of substrate 12 and gate 20 with adeuterium-enriched steam, as will be discussed in more detail below withreference to FIG. 13.

A dielectric material 42 extends over conductively-doped diffusionregions corresponding to source/drain regions 30 and along sidewallsurfaces of gate 22, and merges with gate dielectric 26. Dielectricmaterial 42 can comprise, consist essentially of, or consist of silicondioxide, and can be formed by oxidation of exposed silicon-containingsurfaces of substrate 12 and gate 22 with a deuterium-enriched steam, aswill be discussed in more detail below with reference to FIG. 13.

Transistor constructions 14 and 16 comprise insulative material caps 44and 46, respectively, over gates 20 and 22, and comprise insulativematerial sidewall spacers 48 and 50, respectively, along sidewalls ofthe gates 20 and 22. The caps and spacers can comprise any suitableelectrically insulative compositions, and in particular aspects cancomprise, consist essentially of, or consist of silicon nitride.

The isolation region 18 comprises electrically insulative materials 52,54 and 56 formed within a trench extending within substrate 12.Electrically insulative material 52 can, for example, comprise, consistessentially of, or consist of silicon dioxide formed by oxidation ofsemiconductor material substrate 12 under deuterium-enriched steam, aswill be discussed in more detail below with reference to FIG. 4.Electrically insulative material 54 can, for example, comprise, consistessentially of, or consist of silicon nitride. Electrically insulativematerial 56 can, for example, comprise, consist essentially of, orconsist of silicon dioxide. The shown isolation region can correspond toa so-called shallow trench isolation region.

The construction of FIG. 1 is provided to diagrammatically illustratevarious oxides which can be formed in accordance with exemplarymethodology of the present invention. The illustration of FIG. 1 is fordiagrammatic purposes only, and it is to be understood that thetransistor devices 14 and 16 and isolation region 18 are representativeof classes of devices which can be formed over a semiconductorsubstrate. Specifically, transistor device 14 represents a class ofdevices which can be formed to have a relatively thin gate dielectric,transistor device 16 represents a class of devices which can be formedto have a relatively thick gate dielectric, and isolation region 18represents a class of structures which can be utilized to electricallyisolate adjacent transistor devices from one another. The variousdevices can be formed in the arrangement of FIG. 1, or can be formed inother arrangements, as will be understood by persons of ordinary skillin the art. Exemplary methods of forming the various classes ofstructures of the FIG. 1 construction are described with reference toFIGS. 2-14. In referring to FIGS. 2-14, similar numbering will be usedas was utilized above in describing FIG. 1, where appropriate.

Referring to FIG. 2, substrate 12 is shown at a preliminary processingstage. Substrate 12 can correspond to any suitable semiconductorsubstrate, including, for example, bulk monocrystalline silicon, asilicon-on-insulator assembly, etc. Although the semiconductor substrate12 is described as comprising silicon, it is to be understood that theinvention also encompasses aspects in which the substrate comprisesother semiconductor materials either in addition to, or alternativelyto, silicon. Such other semiconductor materials can include, forexample, germanium. The substrate 12 has an uppermost surface 13comprising semiconductor material. Although substrate 12 is shown havinga homogeneous composition, it is to be understood that substrate 12 cancomprise multiple materials having different compositions relative toone another. Regardless, substrate 12 will typically comprise anuppermost surface 13 containing a semiconductor composition.

Referring next to FIG. 3, an opening 100 is etched through the uppermostsurface 13 of substrate 12. The opening 100 can correspond to a trenchwhich extends longitudinally into and out of the page relative to theshown FIG. 3 cross-section. Opening 100 is surrounded by a periphery 101of semiconductor material of substrate 12. In particular aspects,periphery 101 and surface 13 can comprise, consist essentially of, orconsist of silicon.

Referring next to FIG. 4, semiconductor material of surface 13 andperiphery 101 is subjected to thermal oxidation to form an oxide 52extending across the upper surface 13 and within the opening 100. Oxide52 can, in particular aspects of the invention, comprise, consistessentially of, or consist of silicon dioxide. The oxide 52 ispreferably formed by exposure of surfaces 13 and 101 to adeuterium-enriched steam. The deuterium-enriched steam is defined tocomprise a greater isotopic abundance of deuterium relative to otherhydrogen isotopes than the naturally-occurring isotopic abundance ofdeuterium. In particular aspects, the isotopic abundance of deuteriumrelative to other hydrogen isotopes within the steam will be greaterthan 0.02%, at least about 1%, at least about 10%, at least about 25%,at least about 50%, at least about 75%, or even about 100%. The exposureto the deuterium-enriched steam can occur within a reaction chamber, andthe deuterium-enriched steam can, in particular aspects, be formed in-situ within the chamber from deuterium-enriched molecular hydrogen andO₂. As will be understood by persons of ordinary skill in the art,molecular hydrogen is H₂, and accordingly deuterium-enriched molecularhydrogen comprises various combinations of D₂, DH and H₂, with therelative proportions of the various hydrogen isotopes varying dependingon among other things, the level of deuterium enrichment of themolecular hydrogen. The exposure to the deuterium-enriched steam cancomprise any suitable method, and can be utilized with batch systems aswell as with single wafer systems.

The utilization of deuterium-enriched steam to form oxide 52 providesadvantages relative to utilization of regular steam (i.e., steam whichis not enriched in deuterium) in that there will typically be somedangling silicon bonds generated during formation of the oxide, andhydrogen isotopes from the steam will adhere to the silicon through suchdangling bonds. It can be advantageous if deuterium is adhered to thesilicon rather than hydrogen, in that deuterium-to-silicon bonds be moreresilient to vibrationally-induced breakage than silicon-to-hydrogenbonds. Specifically, the vibrational energy states ofsilicon-to-deuterium bonds can be better-suited for dissipating energywithout breakage of the bonds than can be the vibrational energy statesof silicon-to-hydrogen bonds. In addition, since deuterium is a heavierelement than hydrogen, it diffuses less in silicon than hydrogen.Therefore, if a Si—D bond were to break (due to, for example, highcurrent density and/or high electric fields), “D” stays relatively closeto the silicon dangling bond, increasing the probability of Si—D bondformation and resulting re-passivation.

Referring next to FIG. 5, the oxide 52 can be considered to be a linerextending within trench 100. A film 54 is formed over the liner andwithin the trench to narrow the trench, and subsequently an insulativematerial 56 is formed over film 54 to fill the narrowed trench. Inparticular aspects, liner 52 can comprise, consist essentially of, orconsist of silicon dioxide; film 54 can comprise, consist essentiallyof, or consist of silicon nitride; and insulative material 56 cancomprise, consist essentially of, or consist of silicon dioxide. Film 54and insulative material 56 can be formed by any suitable methods,including, for example, atomic layer deposition (ALD) and/or chemicalvapor deposition (CVD).

Referring to FIG. 6, construction 10 is subjected to planarization,(such as, for example, chemical-mechanical polishing) to remove layers52, 54 and 56 from over surface 13 of substrate 12 while leaving theinsulative materials 52, 54 and 56 within trench 100. Such completesformation of isolation region 18. The planarization utilized to removematerials 52, 54 and 56 from over surface 13 can stop at the initialelevational level of surface 13, or can remove some of substrate 12 sothat the elevational level of surface 13 of FIG. 6 is beneath thestarting elevational level of such surface in the preliminary processingstage of FIG. 2.

FIGS. 7-10 describe formation of the gate dielectric materials 24 and 26of FIG. 1. Referring to FIG. 7, construction 10 is shown at a processingstage subsequent to that of FIG. 6, and specifically is shown afteroxide 26 is formed across upper surface 13 of substrate 12. Oxide 26 ispreferably formed by exposing upper surface 13 of substrate 12 todeuterium-enriched steam to thermally grow material 26, and can beformed under conditions identical to those discussed above withreference to FIG. 4 for growing the oxide material 52. Material 26 can,in particular aspects, comprise, consist essentially of, or consist ofsilicon dioxide, and can be formed to a thickness of at least about 50Å. Although material 26 is not shown extending across isolation region18, it is to be understood that the layer can extend laterally over theisolation region in some aspects of the invention, and further that someof the electrically-insulative materials of the isolation region (suchas, for example, a silicon nitride layer 54) can be thermally oxidizedunder the conditions utilized to oxidize surface 13. The advantages ofutilizing deuterium-enriched steam for forming oxide 26 are similar tothose discussed above relative to formation of oxide 52.

Referring to FIG. 8, a masking material 110 is formed over oxide 26 andpatterned to protect a segment of oxide 26 while leaving another segmentexposed. Masking material 110 can comprise, for example, photoresist,and can be patterned utilizing photolithographic processing. The shownpatterned mask of material 110 extends across isolation region 18 toprotect the materials of such isolation region from a subsequent etch.

Referring next to FIG. 9, exposed portions of oxide 26 are subjected toan etch to remove such exposed portions from over substrate 12.

Referring next to FIG. 10, oxide 24 is formed over the exposed region ofsubstrate 12, and mask 110 is removed. Oxide 24 can be formed by thermaloxidation of surface 13 of substrate 12 utilizing deuterium-enrichedsteam under conditions similar to those utilized for forming oxide 26.However, oxide 24 is shown formed to a thickness different than that ofoxide 26. Specifically, oxide 24 is shown formed to be thinner thanoxide 26. In particular aspects, oxide 24 can be from about 25 Å thickto about 40 Å, and accordingly it will be at least about 15 Å thinnerthan oxide 26. As indicated above in describing FIG. 1, the utilizationof a different thickness gate oxide for some transistors than others canenable threshold voltages of the various transistors to be specificallytailored for particular applications. Specifically, a transistor devicehaving a thin gate dielectric can have a different threshold voltagethan a transistor device having a thick gate dielectric. Frequently,some of the transistor devices formed across a semiconductor substratewill have different functions than others, and the optimal thresholdvoltage of the various transistors will vary depending on the functionsof the transistors. Accordingly, it can be advantageous to be able totailor the threshold voltages of the various transistors.

The mask 110 can be removed before or after the thermal oxidationutilized to form oxide 24. If the mask is removed before such thermaloxidation, there can be an increase in the thickness of oxide 26occurring during the thermal oxidation utilized to form oxide 24. Forinstance, if oxide 24 is formed to be about 35 Å thick, and oxide 26 wasinitially 50 Å thick, the oxide 26 can grow to be about 58 Å thickduring the thermal oxidation utilized to form oxide 24. Oxides 26 and 24can be referred to as first and second oxides, respectively, in order todistinguish the oxides from one another in referring to some aspects ofthe invention.

Referring next to FIG. 11, gate material 120 and capping material 122are formed over substrate 12, and specifically over oxide regions 24 and26. The material 120 can comprise any suitable composition orcombination of compositions for forming electrically conductivetransistor gates, and in particular aspects will include at least aportion which comprises, consists essentially of, or consists ofconductively-doped semiconductor material (such as, for example,conductively-doped silicon). Capping material 122 can comprise anysuitable electrically insulative composition or combination ofcompositions, and in particular aspects will comprise, consistessentially of, or consist of silicon nitride.

A patterned mask 124 is formed over layers 120 and 122. Mask 124 cancomprise, for example, photoresist patterned utilizing photolithographicprocessing.

Referring next to FIG. 12, a pattern from mask 124 (FIG. 11) istransferred to underlying materials 24, 26, 120 and 122, andsubsequently mask 124 is removed. The patterned material 120 formstransistor gates 20 and 22, and the patterned material 122 formselectrically insulative caps 44 and 46. Though gates 20 and 22 are shownformed from the same electrically conductive material 120 as oneanother, it is to be understood that the gates can also be formed fromdifferent electrically conductive materials relative to one another sothat the gates have different compositions relative to one another.Similarly, the caps 44 and 46 can be formed from the same materials asone another (as shown), or in other aspects can be formed from differentelectrically insulative materials relative to one another.

Lightly-doped source/drain regions 29 and 33 are shown implanted afterthe patterning of gates 20 and 22 so that the source/drain regions areself-aligned relative to the gates. It is to be understood that thesource/drain regions can be implanted at other processing stages inaddition to, or alternatively to, the shown processing stage.

Referring next to FIG. 13, construction 10 is subjected to thermaloxidation which forms oxide 40 over source/drain regions 29 and alongsidewalls of gate 20, and which forms oxide 42 over source/drain regions33 and along sidewalls of gate 22. The thermal oxidation preferablycomprises exposure of substrate 10 to deuterium-enriched steam, andprocessing similar to that discussed previously with reference toformation of oxide 52 of FIG. 4. The composition of oxides 40 and 42depends on the compositions of the surfaces which are thermally oxidizedto form oxides 40 and 42. In particular aspects, oxides 40 and 42 cancomprise, consist essentially of, or consist of silicon dioxide. Theformation of oxides 40 and 42 transforms gates 20 and 22 into so-calledsmiling gate constructions, or in other words rounds the lowermostcorners of the gates. Such can be advantageous for improving performanceand reliability of transistors comprising the gates, as will beunderstood by persons of ordinary skill in the art. An advantage ofutilizing deuterium-enriched steam for forming oxides 40 and 42 issimilar to the advantage discussed above with reference to formation ofoxide 52.

In the shown aspect of the invention, oxides 40 and 42 are formed overconductively-doped regions 29 and 30 of substrate 12, and specificallyare formed from surfaces of the conductively-doped regions. It is to beunderstood that the invention encompasses other aspects in which theconductivity-enhancing dopant of the source/drain regions is notprovided prior to the oxidation of a surface which will ultimately beover such source/drain regions. Regardless, substrate 12 can beunderstood to have locations therein where source/drain regions willultimately be formed, and such locations can be referred to assource/drain region locations. The oxidation to form regions 40 and 42can thus be understood to oxidize portions of substrate 12 correspondingto uppermost surfaces of source/drain region locations.

Referring next to FIG. 14, construction 10 is illustrated afterformation of sidewall spacers 48 and 50, and after the implant ofheavily-doped source/drain regions 27 and 31. The spacers 48 and 50 canbe formed by, for example, forming a layer of insulative material acrossa surface of construction 10 and subsequently subjecting such insulativematerial to anisotropic etching. The heavily-doped source/drain regions27 and 31 can be implanted after formation of spacers 48 and 50 so thatthe heavily-doped source/drain regions are self-aligned relative to thelaterally outward edges of the spacers. The source/drain regions 27 and31 can be simultaneously implanted in applications in which thesource/drain regions 27 are identical to the source/drain regions 31. Inother applications, source/drain regions 27 and 31 can be sequentiallyimplanted relative to one another. If the regions are implantedsequentially relative to one another, a mask can be utilized to blockthe location of either source/drain regions 27 or source/drain regions31 while the other of the source/drain regions is implanted, andsubsequently another mask can be utilized to block the implantedsource/drain regions while the remaining source/drain regions areimplanted.

The construction of FIG. 14 is identical to that of FIG. 1. Any of theoxides 24, 26, 40, 42 and 52 can be formed by thermal oxidation withdeuterium-enriched steam. Preferably, at least two of the oxides areformed by thermal oxidation with deuterium-enriched steam, and even morepreferably, all of the oxides are formed by thermal oxidation withdeuterium-enriched steam. It is found that the improvements obtained byutilizing deuterium-enriched steam can enhance one another so that thereis an advantageous improvement obtained in forming multiple oxides fromdeuterium-enriched steam beyond the simple addition of improved effects.In other words, there can be synergy between the improvements obtainedthrough using deuterium-enriched steam for forming multiple oxides.

In the shown aspect of the invention, all of the oxide of materials 24,26, 40, 42 and 52 is formed by thermal oxidation, but it is to beunderstood that the thicknesses of the various oxides can be increasedby adding additional insulative layers onto the oxides after the thermaloxidation. Accordingly, the invention encompasses aspects (not shown) inwhich only portions of one or more of the oxides 24, 26, 52, 40 and 42are formed by thermal oxidation, and in which other portions aresubsequently deposited onto the portions formed by thermal oxidation.The amount of a particular oxide formed by thermal oxidation with adeuterium-enriched steam can vary from an entirety of the oxide, tosubstantially all of the oxide, to a predominate portion of the oxide,to less than a predominate portion of the oxide.

FIG. 15 shows the construction of FIG. 14 after subsequent processinghas been conducted to form one or more insulative masses over transistorconstructions 14 and 16 (with an exemplary insulative mass beingrepresented by mass 200), and to form one or more conductive layers overthe transistor constructions (with an exemplary conductive layer beingillustrated by the layer 202). The conductive layers can correspond toso-called metal I, metal II, metal III, etc. layers.

The source/drain regions 28 and 30 of the transistor constructions areshown electrically connected with circuit devices 204, 206, 208 and 210.In particular aspects, the transistor constructions can be incorporatedinto dynamic random access memory (DRAM) arrays, and accordingly eachtransistor will have a source/drain region connected to a bitline, andanother source/drain region connected to a charge-storage device (suchas, for example, a capacitor). In other aspects, one or both of thetransistors can be incorporated into logic devices or other circuitry.

The shown conductive layer 202 can correspond to an uppermost conductivelayer ultimately formed over construction 10, and in particular aspectscan correspond to the uppermost metal layer. A passivation layer 220 isformed over conductive layer 202. Passivation layer 220 can comprise,for example, hydrogen-enriched silicon nitride. The hydrogen of thehydrogen-enriched silicon nitride layer 220 can comprise about a naturalisotopic abundance of deuterium, or can comprise a greater concentrationof deuterium than the natural isotopic abundance of deuterium. Inparticular aspects, the hydrogen-enriched silicon nitride layer cancomprise at least a two-fold greater concentration of deuterium than anatural isotopic abundance of deuterium, and in other aspects cancomprise at least a ten-fold greater concentration of deuterium than thenatural isotopic abundance of deuterium. However, it can be preferredthat the layer 220 comprise only the natural isotopic abundance ofdeuterium, in that it is generally found that there is little benefit tohaving additional deuterium within the hydrogen-enriched silicon nitridelayer, and it is significantly more expensive to form thesilicon-enriched nitride layer 220 to have a concentration of deuteriumhigher than the natural abundance of deuterium.

The oxides formed in the processing of FIGS. 2-14 can have defectstherein which are introduced during formation of the oxides, or whichare introduced during subsequent processing of construction 10. Suchdefects can be alleviated through passivation conducted at a lateprocessing stage. For instance, the construction 10 of FIG. 15 can beexposed to an anneal while also being exposed to a passivating ambient230. The anneal can be referred to as an alloy anneal, in that one ofthe aspects of the anneal can be to treat various metal alloys withinconstruction 10 to improve various properties of the alloys. The annealcan be conducted at a temperature of, for example, at least about 350°C., and typically will be conducted at a temperature of from about 350°C. to about 450° C. (with an exemplary temperature being from about 400°C. to about 425° C.) at a pressure equal to or greater than atmosphericpressure. The passivating ambient 230 diffuses into construction 10during the anneal, and can be utilized to cure various defects whichwould otherwise be present in structures of construction 10. Forinstance, the ambient utilized during the anneal can comprise componentswhich diffuse into construction 10 to cure defects associated withoxides and other dielectric materials. It can be preferred that ambient230 be a deuterium-enriched ambient, as such can offer advantages forpassivating construction 10 over those of non-deuterium enrichedambients. In particular aspects, the ambient will comprisedeuterium-enriched molecular hydrogen, and specifically will compriseone or both of D₂ and DH.

Utilization of a deuterium-enriched ambient 230 during passivation canprovide synergistic effects in combination with the utilization ofdeuterium-enriched steam during formation of oxides. Specifically, it isfound that if a non-deuterium-enriched ambient is utilized during thepassivation, some of the advantages that would otherwise be manifestedfrom utilization of deuterium-enriched steam during formation of thevarious oxides of construction 10 can be reduced or even eliminated. Incontrast, if a deuterium-enriched ambient is utilized during thepassivation, the advantages achieved through utilization ofdeuterium-enriched steam during formation of the oxides can be enhanced.In some aspects, it is found that devices formed utilizingdeuterium-enriched steam for formation of oxides are less than adequateto achieve desired tolerances, and that it is the combination ofutilization of deuterium-enriched steam during formation of oxides andthe utilization of deuterium-enriched ambients during passivation thatachieves device characteristics suitable to be within desired tolerancesof the devices.

The invention has numerous aspects achievable by utilization ofdeuterium-enriched steam during oxidation and/or utilization of adeuterium-enriched ambient during passivation. In some aspects, theinvention can be understood as utilization of deuterium-enriched steamduring any or all thermal oxidations utilized for fabrication of asemiconductor construction, and such aspects can be coupled withutilization of deuterium-enriched ambients during passivation of theconstruction. In particular aspects, the invention can be understood asincluding methods of forming semiconductor constructions wherein two ormore separate thermal oxidation steps are conducted in the presence ofdeuterium-enriched steam and/or in which at least one thermal oxidationstep is conducted in the presence of deuterium-enriched steam and inwhich passivation of a semiconductor construction comprising the oxideformed from the deuterium-enriched steam is conducted while exposing theconstruction to a deuterium-enriched ambient.

Semiconductor constructions formed in accordance with methodology of thepresent invention can advantageously have oxides which are more stableand less likely to become depassivated and electrically active afterthermal stress or electrical stress than would structures formed withoututilization of either or both of deuterium-enriched steam during thermaloxidation and deuterium-enriched ambients during passivation.

Methodology of the present invention can be incorporated intofabrication of any suitable transistor structure, including planar andnon-planar structures. For instance, methodology of the presentinvention can be incorporated into fabrication of multi-gate devices,finFET devices, recessed access devices, gate-surround (e.g.,gate-all-around) vertical transistors, etc. Devices having largeinterface areas can significantly benefit from passivation achievedthrough methodologies of the present invention.

The oxides formed in particular aspects of the invention can be referredto as “deuterated oxides”. Such oxides can correspond to thermally-grownsilicon dioxide, and can be utilized as, for example, gate oxide,re-oxidation stops, and thin buffer oxides (such as silicon dioxide)used in conjunction with high-k dielectric materials (such as, forexample, hafnium oxide, aluminum oxide, etc.).

Numerous improvements in device performance can be achieved utilizingdeuterated materials formed in accordance with various methodologies ofthe present invention. Such improvements can include, for example,improvement in refresh performance, performance of weak refresh bits inthe tail distribution, and improvement in diode leakage in diodes withinterfaces to dielectrics.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1-64. (canceled) 65: A method of forming a semiconductor construction,comprising: forming one or more oxides over a semiconductor material byexposing the material to steam having an isotopic abundance of deuteriumrelative to other hydrogen isotopes of greater than 0.02%; forming ahydrogen-enriched silicon nitride layer over the one or more oxides; andafter forming the hydrogen-enriched silicon nitride layer, annealing theone or more oxides at a temperature of greater than or equal to about350° C. under an ambient having an isotopic abundance of deuteriumrelative to other hydrogen isotopes of greater than 0.02%; deuteriumfrom the ambient diffusing through the hydrogen-enriched silicon nitridelayer to the one or more oxides during the passivating. 66: The methodof claim 65 wherein one or both of the ambient and the steam comprisesan isotopic abundance of deuterium relative to other hydrogen isotopesof at least about 1%. 67: The method of claim 65 wherein one or both ofthe ambient and the steam comprises an isotopic abundance of deuteriumrelative to other hydrogen isotopes of at least about 10%. 68: Themethod of claim 65 wherein one or both of the ambient and the steamcomprises an isotopic abundance of deuterium relative to other hydrogenisotopes of at least about 25%. 69: The method of claim 65 wherein oneor both of the ambient and the steam comprises an isotopic abundance ofdeuterium relative to other hydrogen isotopes of at least about 50%. 70:The method of claim 65 wherein one or both of the ambient and the steamcomprises an isotopic abundance of deuterium relative to other hydrogenisotopes of at least about 75%. 71: The method of claim 65 wherein oneor both of the deuterium-enriched ambient and the deuterium-enrichedsteam comprises an isotopic abundance of deuterium relative to otherhydrogen isotopes of about 100%. 72: The method of claim 65 wherein thehydrogen of the hydrogen-enriched silicon nitride layer comprises abouta natural isotopic abundance of deuterium. 73: The method of claim 65wherein the hydrogen of the hydrogen-enriched silicon nitride layercomprises a greater concentration of deuterium than the natural isotopicabundance of deuterium. 74: The method of claim 65 wherein the hydrogenof the hydrogen-enriched silicon nitride layer comprises at least atwo-fold greater concentration of deuterium than the natural isotopicabundance of deuterium. 75: The method of claim 65 wherein the hydrogenof the hydrogen-enriched silicon nitride layer comprises at least aten-fold greater concentration of deuterium than the natural isotopicabundance of deuterium.